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Ordering number : EN5964
CMOS IC
LC75750E, 75750W
1/3 Duty VFD Driver
Overview
The LC75750E and LC75750W are 1/3 duty VFD drivers that can be used for electronic tuning frequency display and other applications under the control of a microcontroller. These products can directly drive VFDs with up to 264 segments.
Package Dimensions
unit: mm 3151-QFP100E
[LC75750E]
Features
* 264 segment outputs. * Noise reduction circuits are built into the output drivers. * Serial data input supports CCB format communication with the system controller. * Dimmer can be controlled by serial data input. * High generality since display data is displayed without the intervention of a decoder. * All segments can be turned off with the BLK pin. unit: mm 3181B-SQFP100
[LC75750W]
SANYO: QFP100E (QIP100E)
SANYO: SQFP100
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
101698RM (OT) No. 5964-1/13
LC75750E, 75750W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter Maximum supply voltage Symbol VDD max VFL max VIN1 VIN2 VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg VDD VFL DI, CL, CE, BLK OSCI S1 to S88, G1 to G3 OSCO S1 to S88 G1 to G3 Ta = 85C (LC75750E) Allowable power dissipation Operating temperature Storage temperature Ta = 85C (LC75750W) Conditions Ratings -0.3 to +6.5 -0.3 to +21.0 -0.3 to +6.5 -0.3 to VDD +0.3 -0.3 to VFL +0.3 -0.3 to VDD +0.3 6 60 500 450 -40 to +85 -50 to +150 Unit V V V V V V mA mA nW mW C C
Input voltage
Output voltage
Output current
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 4.5 to 5.5V, VSS = 0V
Parameter Symbol VDD VFL VIH1 VIH2 VIL fOSC ROSC COSC toL toH tds tdh tcp tcs tch tc VDD VFL DI, Cl, CE, BLK OSCI DI, CL, CE, BLK, OSCI OSCI, OSCO OSCI, OSCO OSCI, OSCO CL : Figure 1 CL : Figure 1 DI, CL : Figure 1 DI, CL : Figure 1 CE, CL : Figure 1 CE, CL : Figure 1 CE, CL : Figure 1 BLK, CE : Figure 3 Conditions Ratings min 4.5 8 0.8 VDD 0.8 VDD 0 0.9 2.2 15 160 160 160 160 160 160 160 10 2.4 12 33 typ 5.0 12 max 5.5 18 5.5 VDD 0.2 VDD 3.7 47 100 Unit V V V V V MHz K pF ns ns ns ns ns ns ns s
Supply voltage
Input high-level voltage Input low-level voltage Guaranteed oscillator range Recommended external resistance Recommended external capacitance Low level clock pulse width High level clock pulse width Data setup time Data hold time CE wait time CE setup time CE hold time BLK switching time
Electrical Characteristics in the Allowable Operating Ranges
Parameter Symbol IIH1 IIH2 IIL VOH1 Output high-level voltage VOH2 VOH3 Output low-level voltage Oscillator frequency Hysteresis voltage Current drain VOL1 VOL2 fOSC VH IDD Conditions DI, CL, CE, BLK : VIN = 5.5V OSCI : VIN = VDD DI, CL, CE, BLK, OSCI : VIN = 0V S1 to S88 : IO = -2 mA G1 to G3 : IO = -50 mA OSCO : IO = -0.5 mA S1 to S88, G1 to G3 : IO = 50 A OSCO :IO = 0.5mA ROSC = 12 k, COSC = 33 pF DI, CL, CE, BLK Outputs open : fOSC = 2.4 MHz 2.4 0.1 VDD 10 -5 VFL - 0.6 VFL - 1.3 VDD - 2.0 0.5 2.0 Ratings min typ max 5 5 Unit A A A V V V V V MHz V mA
Input high-level current Input low-level current
No. 5964-2/13
LC75750E, 75750W * When CL is stopped at the low level
* When CL is stopped at the high level
Figure 1
No. 5964-3/13
LC75750E, 75750W Pin Assignment (Top view)
No. 5964-4/13
LC75750E, 75750W Block Diagram
Pin Functions
Pin No. 4 96 93 95 94 Pin VFL VDD VSS OSCI OSCO Function Driver block power supply. A voltage of between 8.0 and 18.0 V must be supplied. Logic block power supply. A voltage of between 4.5 and 5.5 V must be supplied. Power supply. Must be connected to the system ground. Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor to these pins. Display off control input. BLK = L (VSS) ...........Display off (S1 to S24, G1 to G3 = L) BLK = H (VDD) ..........Display on Note that serial data can be transferred while the display is turned off. Serial data transfer inputs. These pins must be connected to the system microcontroller. CL : Synchronization clock DI : Transfer data CE : Chip enable I O O GND OPEN OPEN I/O -- -- -- I O Handling when unused -- -- -- GND OPEN
97
BLK
I
GND
99 100 98 1 to 3
CL DI CE
G1 to G3 Digit outputs. The frame frequency fo is (fOSC/6144)Hz.
92 to 5 S1 to S88 Segment outputs for displaying the display data transferred by serial data input
No. 5964-5/13
LC75750E, 75750W Serial Data Transfer Format * When CL is stopped at the low level
CCB address 8 bits
Display data 88 bits
Control data 14 bits
DD 2 bits
CCB address 8 bits
Display data 88 bits
DD 2 bits
CCB address 8 bits
Display data 88 bits
DD 2 bits * : don't care DD : direction data
* When CL is stopped at the high level
CCB address 8 bits
Display data 88 bits
Control data 14 bits
DD 2 bits
CCB address 8 bits
Display data 88 bits
DD 2 bits
CCB address 8 bits
Display data 88 bits
DD 2 bits * : don't care DD : direction data
Figure 2
No. 5964-6/13
LC75750E, 75750W CCB address : Transfer 00100001B (84H) as shown in Figure 2 DM0 to DM9 : Dimmer data This data controls the duty of the G1 to G3 digit output pins, and consists of 10 bits with DM0 being the LSB. Note that the intensity of the display can be adjusted by controlling the duty of the G1 to G3 digit output pins. The relationship between the dimmer data and the dimmer value is as follows.
DM9 0 0 0 DM8 0 0 0 DM7 0 0 0 DM6 0 0 0 DM5 0 0 0 DM4 0 0 0 DM3 0 0 0 DM2 0 0 0 DM1 0 0 1 DM0 0 1 0 Dimmer value (t4/t3) 0/1024 1/1024 2/1024
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
1020/1024 1021/1024 1022/1024 Not used
t3, t4 : See Figure 4.
D1 to D88
:
D89 to D176
:
D177 to D264 :
Display data for the G1 digit output pin. Dn (n = 1 to 88) = 1 : On Dn (n = 1 to 88) = 0 : Off Display data for the G2 digit output pin. Dn (n = 89 to 176) = 1 : On Dn (n = 89 to 176) = 0 : Off Display data for the G3 digit output pin. Dn (n = 177 to 264) = 1 : On Dn (n = 177 to 264) = 0 : Off
No. 5964-7/13
LC75750E, 75750W Correspondence between Display Data (D1 to D264) and Segment Output Pins
Segment output pins S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 G1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 G2 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 G3 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 Segment output pins S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 G1 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 G2 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 G3 D207 D208 D209 D210 D211 D212 D213 D214 D215 D216 D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 Segment output pins S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 G1 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 G2 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 G3 D237 D238 D239 D240 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264
Example : Segment output pin S11 is controlled as follows :
Display data D11 0 0 0 0 1 1 1 1 D99 0 0 1 1 0 0 1 1 D187 0 1 0 1 0 1 0 1 The segments corresponding to the G1, G2, and G3 digit output pins are off The segments corresponding to the G3 digit output pin are on The segments corresponding to the G2 digit output pin are on The segments corresponding to the G2 and G3 digit output pins are on The segments corresponding to the G1 digit output pin are on The segments corresponding to the G1 and G3 digit output pins are on The segments corresponding to the G1 and G2 digit output pins are on The segments corresponding to the G1, G2, and G3 digit output pins are on Segment output pin S11 state
No. 5964-8/13
LC75750E, 75750W BLK and the Display Control Since the IC internal data (D1 to D264 and the control data) is undefined when power is first applied, the display is off (S1 to S88, G1 to G3 = low) by setting the BLK pin low at the same time as power is applied. Then, meaningless display at power on can be prevented by transferring all 336 bits of serial data from the controller and setting BLK pin high after the transfer completes while the display is off. (See Figure 3.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 3.) * Power on : Logic block power supply (VDD) on Driver block power supply (VFL) on * Power off : Driver block power supply (VFL) off Logic block power supply (VDD) off
VDD
VFL
BLK
CE Transfer of display and control data Internal data (D1 to D88, control data) Undefined Defined Undefined
Internal data (D89 to D176)
Undefined
Defined
Undefined
Internal data (D177 to D264)
Undefined
Defined
Undefined
ton > 0 toff1 > 0 toff2 > 0 (toff1 > toff2) tc...10 s min
Figure 3
No. 5964-9/13
LC75750E, 75750W Output Waveforms (S1 to S88)
G1
G2
G3
S1 to S88 output waveforms on G1 side being lighted
S1 to S88 output waveforms on G2 side being lighted
S1 to S88 output waveforms on G3 side being lighted
S1 to S88 output waveform on G1 and G2 sides being lighted
S1 to S88 output waveform on G1 and G3 sides being lighted
S1 to S88 output waveform on G2 and G3 sides being lighted
S1 to S88 output waveform on G1 to G3 sides being lighted
S1 to S88 output waveform on G1 to G3 sides being unlighted
No. 5964-10/13
LC75750E, 75750W Relationship between Segment and Digit outputs
Example 1
Example 2
Example 3
Figure 4 * Consider the examples shown in Figure 4, where display data is set up so that the segment outputs S1 to S88 output VSS level on the G1 and G3 digit output timing and VFL level on the G2 digit output timing. (Here, the G2 side being lighted) The relationship between the time t3 and the oscillator frequency fOSC is t3 = 2048/fOSC. * The digit output G1 to G3 waveforms in Example 1 are output when the dimmer data (DM0 to DM9) are set to 3FEH. The relationship between the time t1 and the oscillator frequency fOSC is t1=2/fOSC. Note that the time t1 and the time t2 are the same period in Example 1. * The digit output G1 to G3 waveforms in Example 2 are those when the dimmer data (DM0 to DM9) are set to a smaller value. Although the time t1 does not change, the time t2 becomes longer. When the dimmer data (DM0 to DM9) are set to 1FFH and the oscillator frequency fosc is 2.4 [MHz], then the time t2 is : t2 = t3 - t1 x (1FFH + 1) 1024 = ---- fOSC = 0.43[ms] * When the dimmer data (DM0 to DM9) are set to an even smaller value, the time t2 becomes even longer, as in example 3. Note that the time t1 does not change here, either.
No. 5964-11/13
LC75750E, 75750W Sample Application Circuit
From the controller
Notes on the segment and digit waveforms
Segment waveform
Digit waveform 1
Digit waveform 2
Figure 5 The segment waveform is distorted by the VFD panel used and the wiring, and furthermore, in the case of being used with essentially no dimming as in the digit waveform 1, as shown in Figure 5, the VFD panel glow dimly. By carefully considering the segment waveform, it can be seen that this problem can be resolved by applying an adequate amount of dimming, as shown in digit waveform 2. Notes on transferring display data from the controller Since display data is transferred in three operations as shown in Figure 2, we recommend that all display data be transferred within 30 [ms] to prevent degradation of the visual quality of the displayed image.
VFD panel (up to 264 segments)
No. 5964-12/13
LC75750E, 75750W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1998. Specifications and information herein are subject to change without notice. PS No. 5964-13/13

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